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[ak4201] ms1077-e-01 2011/02 - 1 - general description the ak4201 is an audio stereo cap-less headphone amplifie r. the ak4201 eliminat es the need for large dc-blocking capacitors with a built-in charge-pum p circuit. a 100db psrr (p ower supply rejection ratio) is achieved by a built-in r egulator, and 2vrms outputs are availabl e with excellent linearity when the ak4201 is used as a lineout am plifier. the ak4201 is available in ti ny 12-pin uson (2.2 x 2.9mm), saving board space, cost, and r educing component height. feature ? stereo cap-less amplifier (no dc-blocking capacitors required) ? high psrr (100db at 217hz) ? output power: 65 mw x 2ch @ 16 , avdd=pvdd=5.0v, thd+n=-60db 30 mw x 2ch @ 16 , avdd=pvdd=3.3v, thd+n=-60db ? output noise level: 11vrms (ri=20k , rf=30k ) ? line-out level: 2.0vrms @ 5k , avdd=pvdd=5.0v 2.0vrms @ 5k , avdd=pvdd=3.3v ? regulator built-in ? thd+n : -60db @ 16 , 50mw, avdd=pvdd=5.0v -60db @ 16 , 20mw, avdd=pvdd=3.3v -100db @ 5k , 2vrms, avdd=pvdd=5.0v -100db @ 5k , 2vrms, avdd=pvdd=3.3v ? low power shutdown mode 0.1a (typ) ? mute function at shutdown mode: -88db attenuation no external component is required ? zero offset by ground-referenced output ? pop noise free at power-on/off ? power supply: 2.6v ~ 3.6v or 4.5v ~ 5.5v ? ta: ? 40 85 c ? package: 12pin uson (2.2 x 2.9mm, 0.5mm pitch) stereo cap-less hp-amp ak4201
[ak4201] ms1077-e-01 2011/02 - 2 - block diagram amp charge pump amp avdd pvdd lin rin pvee lout rout vss2 pdn cp cn regulator regulator vss1 a k4201 rf rf ri ri ci ci figure 1. ak4201 block diagram
[ak4201] ms1077-e-01 2011/02 - 3 - ordering guide ak4201eu ? 40 +85 c 12pin uson (2.2mm x 2.9mm, 0.5mm pitch) akd4201 evaluation board for ak4201 pin layout 1 lin top view 2 3 4 12 11 10 9 5 6 8 7 lout avdd vss1 pvdd cn rin rout pvee vss2 pdn cp
[ak4201] ms1077-e-01 2011/02 - 4 - pin/function no. pin name i/o function 1 lin i l-channel analog input 2 lout o l-channel analog output 3 avdd - headphone positive power supply pin 4 vss1 - ground 1 pin 5 pvdd - charge-pump positive power supply pin 6 cn i negative charge-pump capacitor terminal pin 7 cp o positive charge-pump capacitor terminal pin 8 pdn i power-down mode pin ?h?: power-up, ?l?: power-down 9 vss2 - ground 2 pin 10 pvee o charge-pump circuit negative voltage output pin 11 rout o r-channel analog output 12 rin i r-channel analog input note. the pdn pin must not be floated. handling of unused pin the unused i/o pins must be processed appropriately as below. classification pin name setting analog lin, rin, lout, rout connect output pin to input pin when one channel is used and the other is not used. (example) connect the rout pin to the rin pin if rch is not used.
[ak4201] ms1077-e-01 2011/02 - 5 - absolute maximum ratings (vss1=vss2 =0v ( note 1 )) parameter symbol min max units power supplies: analog avdd ? 0.3 6.0 v ( note 2 ) charge pump pvdd ? 0.3 6.0 v input current, any pin except supplies iin - 10 ma input voltage ( note 3 ) vin ? 0.3 (avdd + 0.3) or 6.0 v ambient temperature (powered applied)( note 4 ) ta ? 40 70( note 5) 85( note 6) c storage temperature tstg ? 65 150 c note 1. all voltages are respect to ground. the pdn pin should be held to ?l? when powered-up, and it should be set to ?h? after all power supplies are powered-up. the pdn pin should be held to ?l?, when powered-down. note 2. vss1 and vss2 must be c onnected to the same analog plane. note 3. lin, rin and pdn pin the maximum value is smaller value between (avdd+0.3)v and 6.0v. note 4. pcb wiring density should be 150% or more . device back pad should be connected to ground. note 5. headphone output power should below 65mw/ch. note 6. headphone output power should below 50mw/ch. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. recommend operating conditions (vss1=vss2 =0v ( note 1 )) parameter symbol min typ max units analog, charge pump avdd, pvdd 4.5 2.6 5.0 3.3 5.5 3.6 v power supplies ( note 7) difference avdd ? pvdd -0.3 0 0.3 v parameter symbol min typ max units external input resistance ri 10 - 100 k external feedback resistance rf 10 - 100 k gain range gain -16 - 16 db load resistance (lout, rout pins) r l 16 - - capacitance (lout, rout pins) c l - - 300 pf capacitance (lin, rin pins) csum - - 20 pf note 7. avdd and pvdd must not be in the range from 3.6v to 4.5v. note: akm assumes no responsibility for the usag e beyond the conditions in this datasheet.
[ak4201] ms1077-e-01 2011/02 - 6 - analog characteristics (avdd=pvdd=5.0v) (avdd=pvdd=5.0v; pdn=5.0v; ta=25oc; vss1=vss2=0v; input signal frequency =1khz; measurement band width=10hz 20khz; gain=+3.5db (ri=20k , rf=30k ); headphone-amp: r l =16 ; charge pump circuit external capacitance: c1=c2= 1 f ( figure 3 ), unless otherwise specified) parameter min typ max units output power r l =16 , 0.68vrms input - 65 - mw thd+n 0.68vrms input; po = 65mw @ r l =16 - ? 60 - db 0.60vrms input; po = 50mw @ r l =16 - ? 60 -50 db 1.33vrms input; vo = 2.0vrms @ r l =5k - ? 100 -90 db s/n (signal-to-noise ratio) r l =16 (a-weighted) ( note 8 ) 94 100 - db r l =5k (a-weighted) ( note 9 ) 100 106 - db psrr (power supply rejection ratio) ( note 10 ) 217hz - 100 - db 1khz - 90 - db interchannel isolation r l =16 60 80 - db r l =5k - 100 - db output offset voltage - 0 1 mv start-up time ( note 11 ) - - 50 ms power supplies avdd + pvdd (normal mode; no output) - 4.8 7.2 ma avdd + pvdd (power-down mode, pdn =0v) - 0.1 10 ua note 8. in case of 0.68vrms input (po=65mw). note 9. in case of 1.33vrms input (vo=2vrms). note 10. psr is applied to avdd and pvdd with 300mvpp sine wave. note 11. the time from the pdn pin= ?h? to when the ak4201 can output signals.
[ak4201] ms1077-e-01 2011/02 - 7 - analog characteristics (avdd=pvdd=3.3v) (avdd=pvdd=3.3v; pdn=3.3v; ta=25oc; vss1=vss2=0v; input signal frequency =1khz; measurement band width=10hz 20khz; gain=+3.5db (ri=20k , rf=30k ); headphone-amp: r l =16 ; charge pump circuit external capacitance: c1=c2= 1 f ( figure 3 ), unless otherwise specified) parameter min typ max units output power r l =16 , 0.46vrms input - 30 - mw thd+n 0.46vrms input; po = 30mw @ r l =16 - -60 - db 0.27vrms input; po = 10mw @ r l =16 -60 -50 db 1.33vrms input; vo = 2.0vrms @ r l =5k - -100 -90 db s/n (signal-to-noise ratio) r l =16 (a-weighted) ( note 12 ) 90 96 - db r l =5k (a-weighted) ( note 13 ) 100 106 - db psrr (power supply rejection ratio) ( note 14 ) 217hz - 70 - db 1khz - 70 - db interchannel isolation r l =16 60 77 - db r l =5k - 100 - db output offset voltage - 0 1 mv start-up time ( note 15 ) - - 50 ms power supplies avdd + pvdd (normal mode; no output) - 3.8 5.7 ma avdd + pvdd (power-down mode, pdn =0v) - 0.1 10 a note 12. in case of 0.46vrms input (po=30mw). note 13. in case of 1.33vrms input (vo=2vrms). note 14. psr is applied to avdd and pvdd with 100mvpp sine wave. note 15. the time from the pdn pin= ?h? to when the ak4201 can output signals.
[ak4201] ms1077-e-01 2011/02 - 8 - dc & switching characteristics (ta= -40 85 c; avdd=pvdd=2.6 3.6v or 4.5 5.5v, note 16 ) parameter symbol min typ max units high-level input voltage vih 1.6 - - v low-level input voltage vil - - 0.5 v input leakage current iin - - 2 a power-down (pdn pulse width) tpd 150 - ns note 16. apply to the pdn pin. timing diagram tpd vil pdn vih figure 2. power-down timing
[ak4201] ms1077-e-01 2011/02 - 9 - operation overview charge pump circuit the charge pump operates by the output of a regulator whic h uses pvdd voltage. the negative power supply (pvee) for headphone amplifiers is generated from internal charge pump circuit. the external capacitors are showed in figure 3 . low esr (equivalent series resistance) capacitors with 1uf to 2.2uf (+/-35% or less difference including temperature drift and a deviation over samples) are recommended for c1 and c2. the minimum value of capacitors should be more than 0.65uf if temperature drifts and a deviation over samples are big. pvee pin charge pump circuit cn pin c2: 1uf cp pin headphone-amp negative voltage c1: 1uf vss1 figure 3. charge pump circuit external capacitor headphone-amp (lout/rout pins) power supply voltage for headphone amplifiers is supplied by a regulator for positive power and a charge-pump for negative power. the headphone amplifier output is single-e nded and centered on vss1(0v). therefore, a capacitor for ac-coupling can be removed. the minimum load resistance is 16 ? . the output impedance is 20 ? (typ) when powered-down.
[ak4201] ms1077-e-01 2011/02 - 10 - power-up/down sequence the pdn pin must keep ?l? until all power supply pins (avdd, pvdd) are supplied, and must be set to ?h? after. power supply pdn pin pvee pin lou t/r ou t pins (1) 0v pvee pin output =-3.3v(typ.) 0v 0v (2 ) (3) normal operation(0v common) 0v don?t care normal operation the device in front of ak4201 dac etc don?t care (5) the device in front of ak4201 click noise 0v power up (no signal output) (4) a ta figure 4. power-up/down sequence example (1) the interval from power up to pdn pin = ?l? ?h? ?l? time of 150ns or more is needed to reset the ak4201. the power should be on when the pdn pin = ?l?. the pdn pin should be set to ?h? after power supply (avdd, pvdd) are on. (2) the interval from power-up of the signal source device in front of the ak4201 to the ak4201?s pdn pin transition from ?l? to ?h? the other device should be powered up with no signal (e.g. mute). when a step wave (an instant dc level change) is output from the other device at th e power-up, a high pass filter response wave will occur at ?a? timing of figure 4 , according to the time constant of the input coupling capac itor (ci) and the input resi stor(ri) in front of the ak4201. in order to prevent this pop noise through the ak 4201, a wait time ?ta? is required after the other devices are powered-up. the ak4201 can attenuate pop noises of the other device by a built-in mute circuit during shutdown mode (pdn pin= ?l?). ta calculation example: (in the case of ci =0.22uf, ri = 20k ? ) =0.22u * 20k = 4.4ms ta = * 7.6 = 33ms (when noise level by former device= 2v, response wave level= 1mv. 7.6* is needed) if a waiting time is not sufficient, a pop noise might occur, but there is no problem for the normal operation. (3) the ak4201 is in normal operation 50ms (max) after the pdn pin goes to ?h?. the other device in front of the ak4201 should be still muted during this interval (50ms). (4) the other device in front of the ak4201 should start outputting the signa l after the ak4201 starts normal operation. if click noise is generate d by former device when mute is can celed, it will be output from the ak4201. (5) the pdn pin = ?l?. lout/rout pins short to vss1 with 20 ? (typ.). after 50ms (max.), the pvee pin will be 0v according to a capacitor which connected to pvee and internal resistance (typ. 17.5k ? ). the ak4201 can be powered up again after 150ns or more from the pdn pin = ?l?.
[ak4201] ms1077-e-01 2011/02 - 11 - system design top vie w power supply 4.5 5.5v, 2.6 3.6v dsp or p 10 1 0.1 (+) (+) + 1 lin 2 3 4 5 6 lout av d d vss1 pvdd cn rin rout pvee vss2 pdn cp 12 11 10 9 8 7 0.1 1 0.22 0.22 20k 20k 30k a nalog input a nalog input ci ri rf ci ri + 10 power supply 4.5 5.5v, 2.6 3.6v 30k rf note: 1. the pdn pin should be held to ?l? when powered-up. the pdn pin should be set to ?h? after all power supplies are powered-up. when power-down the ak4201, the pdn pin should be held to ?l?. refer to ?power-up/down sequence? to a void pop noise when power-up/down the ak4201. 1) power-up the power should be on when the pdn pin = ?l?. the pdn pin should be set to ?h? 150ns after all power supplies (avdd, pvdd) are on. 150ns ?l? time or more is needed to reset the ak4201. 2) power-down the ak4201 should be powered-down when the pdn pin = ?l?. 2. 1uf~2.2uf ceramic capacitors (35% including temperatur e characteristics and piece-to-p iece variations) should be connected to between the cp and cn pins, and the vss1 and pvee1 pins, respectively. 3. both lines from the lin pin and rin pin to each input resi stance ri and feedback resistan ce rf should be as short as possible for better psrr. 4. ac coupling capacitors should be connected to lin and rin pins, respectively.
[ak4201] ms1077-e-01 2011/02 - 12 - package 12pin uson (2.2mm x 2.9mm, 0.5mm pitch) 2.2 0.05 2.9 0.05 0.6max 2.9 0.05 0.225 0.05 0.5 0.25 0.05 0.05 m 0.08 0.05 0.175 0.05 2.2 0.05 1.35 0.05 2.6 0.05 exposed pad ? 0.50 au: 0.1um< ni: 65 15um a g: 2.5um< 0.05 s s note) the exposed pad on the bottom surface of the package must be connected to the ground.
[ak4201] ms1077-e-01 2011/02 - 13 - marking 4201 xxxx 1 xxxx: date code (4 digit) date (yy/mm/dd) revision reason page contents 09/05/12 00 first edition 11/02/03 01 specification addition 12 the package drawing was changed. revision history
[ak4201] ms1077-e-01 2011/02 - 14 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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